The process flow for semiconductor fabrication of integrated circuits (ICs) may include front-end-of-line (FEOL), mid-end-of-line (MEOL), and back-end-of-line (BEOL) processes. The FEOL process may include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MEOL process may include gate contact formation. The BEOL processes may include a series of wafer processing steps for interconnecting the semiconductor devices created during the FEOL and MEOL processes. Successful fabrication and qualification of modern semiconductor chip products involves an interplay between the materials and the processes employed. In particular, the formation of conductive material plating for the semiconductor fabrication in the BEOL processes is an increasingly challenging part of the process flow. This is particularly true in terms of maintaining a small feature size. The same challenge of maintaining a small feature size also applies to passive on glass (POG) technology, where high-performance components such as inductors and capacitors are built upon a highly insulative substrate that may also have a very low loss.
Passive on glass devices involve high-performance inductor and capacitor components that have a variety of advantages over other technologies, such as surface mount technology or multi-layer ceramic chips. These advantages include being more compact in size and having smaller manufacturing variations. Passive on glass devices also involve a higher Q (or quality factor) value that meets stringent low insertion loss and low power consumption specifications.